The need for high performance semiconductor chips has continued to increase over the past several years while, at the same time, the amount of area of the chip has decreased. Moreover, in modern integrated circuits, components having different functions need to be integrated on the same chip; for instance, digital circuits are often needed in combination with analog mix-mode circuits and high sensitive receiving circuits need to be integrated with high power transmitting circuits. However, with ever decreasing feature sizes, the integration on the same chip of components performing differing functions (for instance transmitters and receivers) has been revealed as being a very challenging task. In fact, the performance of a chip or unit comprising different components such as, for example noisy and sensitive components, are strongly affected by the crosstalk interferences arising between these components. Accordingly, a very strong isolation is required between the different components of a chip for the purpose of avoiding and/or reducing crosstalk interference therebetween. When integrated circuits are fabricated on a semiconductive bulk (for instance a silicon layer) according to the standard CMOS and/or BiCMOS technologies, several approaches are used for the purpose of obtaining high isolation between the different components of the chip; along these approaches, the triple well and/or guard rings technologies may be cited. Moreover, when standard CMOS and/or BiCMOS manufacturing processes are used, the need for avoiding and/or reducing interference between the components of the chip is also taken into account at the stage of defining the layout of the chip and multiple voltage sources are provided for different portions of the integrated circuit. However, for central processing units (CPU) operating at clock frequencies of up to 1 GHz and above, the prior art solutions usually adopted in combination with standard bulk CMOS and/or BiCMOS manufacturing processes (triple well, guard rings or the like) have revealed to be not satisfactory, since the isolation between the circuit components obtained by means of these solutions is not sufficient and the performances of the chip are still negatively affected by crosstalk interference arising between these components, in particular between adjacent components.
To overcome this drawback, several solutions have been proposed and developed in the art. In particular, since 1998, the use of silicon-on-insulator (SOI) wafers for fabricating integrated circuits has increased significantly. Among other advantages offered, SOI wafers have the potential to improve the performance of CMOS circuits and have become widely used substrates in the manufacturing of integrated circuits.
Typically, a SOI wafer comprises an upper and a lower layer of silicon and a dielectric layer sandwiched therebetween. The upper layer is sometimes referred to as the active layer, the lower layer is sometimes referred to as the bulk and/or handle layer and the dielectric layer is sometimes referred to as a Buried OXide layer (BOX).
In the art, several approaches are known for forming SOI wafers. Depending on the approach used, different materials are selected for forming the sandwiched dielectric layer. For instance, when silicon-on-sapphire (SOS) wafers are formed, a layer of pure aluminum oxide is sandwiched between two layers of silicon. Alternatively, the separation by implanted oxygen approach and/or the wafer bonding (WB) approach can be used for forming SOI wafers, wherein silicon dioxide is used as the dielectric material.
When building chips on SOI wafers, a transistor of the chip can be isolated from another one by lateral oxide regions and these devices are then interconnected in the conventional way.
There are several advantages offered by the SOI technology. First, circuits fabricated on SOI wafers have reduced parasitic capacitance when compared to bulk wafers that may have an additional epitaxially grown silicon layer. Less capacitance translates into lower power consumption or higher speed. Second, SOI devices have improved radiation-induced single-event upset (SEU) immunity, and they are useful for air and space applications. Thirdly, SOI devices are completely free of latch-up. Moreover, the fabrication process on SOI wafers can be simplified by reducing the number of masks by as much as 30%. Finally, higher performances (in terms of speed) are achievable. In terms of crosstalk, this means extremely good isolation from the substrate noise at transistor level.
However, fabricating semiconductor devices on SOI wafers has several drawbacks. SOI technology is a high cost technology; in particular, this is due to the fact that when SOI wafers are used, processes have to be carried out which are much more expensive than the processes carried out for fabricating semiconductor circuits starting from usual bulk silicon layers. Moreover, SOI wafers are much more expensive than standard bulk silicon layers; in particular, fabricating CMOS circuits on SOI wafers in conformity with SOI fabrication techniques requires that the active silicon layer be thinner than 50 nm. Moreover, the active silicon layer must exhibit very stringent surface uniformity (approximately 10 times the surface uniformity required in the case of standard bulk silicon wafers). Finally, transistors on SOI wafers are affected from the floating body effect; in fact, the lower silicon layer is isolated by the intermediate dielectric layer and cannot be easily connected to the front side of the wafer. However, at least one electrical contact to the lower silicon layer has to be provided since a floating layer under the sandwiched dielectric layer may have an unpredictable impact on the devices fabricated on the wafer during operation.
Accordingly, in view of the problems explained above, it would be desirable to provide a method of forming circuits on SOI wafers that may solve or reduce one or more of the problems identified above. In particular, it would be desirable to provide a method of forming circuits on SOI wafers allowing the fabrication of circuits which, on the one hand, are suitable for medium/high frequency applications and, on the other hand, exhibit high substrate isolation and low crosstalk at low cost.